88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
#include "types.h"
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#include "param.h"
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#include "memlayout.h"
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#include "riscv.h"
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void main();
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void timerinit();
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// Entry.S needs one stack per CPU.
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__attribute__((aligned(16))) char stack0[4096 * NCPU];
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// A scratch area per CPU for machine-mode timer interrupts.
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u64 timer_scratch[NCPU][5];
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// Assembly code in kernelvec.S for machine-mode timer interrupt.
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extern void timervec();
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// Entry.S jumps here in machine mode on stack0.
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void
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start()
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{
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// Set M Previous Privilege mode to Supervisor, for mret.
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unsigned long x = r_mstatus();
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x &= ~MSTATUS_MPP_MASK;
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x |= MSTATUS_MPP_S;
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w_mstatus(x);
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// Set M Exception Program Counter to main, for mret.
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// Requires gcc -mcmodel=medany
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w_mepc((u64)main);
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// Disable paging for now.
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w_satp(0);
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// Delegate all interrupts and exceptions to supervisor mode.
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w_medeleg(0xffff);
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w_mideleg(0xffff);
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w_sie(r_sie() | SIE_SEIE | SIE_STIE | SIE_SSIE);
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// Configure Physical Memory Protection to give supervisor mode
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// Access to all of physical memory.
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w_pmpaddr0(0x3fffffffffffffull);
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w_pmpcfg0(0xf);
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// Ask for clock interrupts.
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timerinit();
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// Keep each CPU's hartid in its tp register, for cpuid().
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int id = r_mhartid();
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w_tp(id);
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// Switch to supervisor mode and jump to main().
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asm volatile("mret");
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}
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// Arrange to receive timer interrupts.
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// They will arrive in machine mode at
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// at timervec in kernelvec.S,
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// which turns them into software interrupts for
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// devintr() in trap.c.
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void
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timerinit()
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{
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// Each CPU has a separate source of timer interrupts.
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int id = r_mhartid();
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// Ask the CLINT for a timer interrupt.
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int interval = 1000000; // Cycles; about 1/10th second in qemu.
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*(u64 *)CLINT_MTIMECMP(id) = *(u64 *)CLINT_MTIME + interval;
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// Prepare information in scratch[] for timervec.
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// scratch[0..2] : space for timervec to save registers.
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// scratch[3] : address of CLINT MTIMECMP register.
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// scratch[4] : desired interval (in cycles) between timer interrupts.
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u64 *scratch = &timer_scratch[id][0];
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scratch[3] = CLINT_MTIMECMP(id);
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scratch[4] = interval;
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w_mscratch((u64)scratch);
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// Set the machine-mode trap handler.
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w_mtvec((u64)timervec);
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// Enable machine-mode interrupts.
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w_mstatus(r_mstatus() | MSTATUS_MIE);
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// Enable machine-mode timer interrupts.
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w_mie(r_mie() | MIE_MTIE);
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}
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