ab0db651af
The x86-64 doesn't just add two levels to page tables to support 64 bit addresses, but is a different processor. For example, calling conventions, system calls, and segmentation are different from 32-bit x86. Segmentation is basically gone, but gs/fs in combination with MSRs can be used to hold a per-core pointer. In general, x86-64 is more straightforward than 32-bit x86. The port uses code from sv6 and the xv6 "rsc-amd64" branch. A summary of the changes is as follows: - Booting: switch to grub instead of xv6's bootloader (pass -kernel to qemu), because xv6's boot loader doesn't understand 64bit ELF files. And, we don't care anymore about booting. - Makefile: use -m64 instead of -m32 flag for gcc, delete boot loader, xv6.img, bochs, and memfs. For now dont' use -O2, since usertests with -O2 is bigger than MAXFILE! - Update gdb.tmpl to be for i386 or x86-64 - Console/printf: use stdarg.h and treat 64-bit addresses different from ints (32-bit) - Update elfhdr to be 64 bit - entry.S/entryother.S: add code to switch to 64-bit mode: build a simple page table in 32-bit mode before switching to 64-bit mode, share code for entering boot processor and APs, and tweak boot gdt. The boot gdt is the gdt that the kernel proper also uses. (In 64-bit mode, the gdt/segmentation and task state mostly disappear.) - exec.c: fix passing argv (64-bit now instead of 32-bit). - initcode.c: use syscall instead of int. - kernel.ld: load kernel very high, in top terabyte. 64 bits is a lot of address space! - proc.c: initial return is through new syscall path instead of trapret. - proc.h: update struct cpu to have some scratch space since syscall saves less state than int, update struct context to reflect x86-64 calling conventions. - swtch: simplify for x86-64 calling conventions. - syscall: add fetcharg to handle x86-64 calling convetions (6 arguments are passed through registers), and fetchaddr to read a 64-bit value from user space. - sysfile: update to handle pointers from user space (e.g., sys_exec), which are 64 bits. - trap.c: no special trap vector for sys calls, because x86-64 has a different plan for system calls. - trapasm: one plan for syscalls and one plan for traps (interrupt and exceptions). On x86-64, the kernel is responsible for switching user/kernel stacks. To do, xv6 keeps some scratch space in the cpu structure, and uses MSR GS_KERN_BASE to point to the core's cpu structure (using swapgs). - types.h: add uint64, and change pde_t to uint64 - usertests: exit() when fork fails, which helped in tracking down one of the bugs in the switch from 32-bit to 64-bit - vectors: update to make them 64 bits - vm.c: use bootgdt in kernel too, program MSRs for syscalls and core-local state (for swapgs), walk 4 levels in walkpgdir, add DEVSPACETOP, use task segment to set kernel stack for interrupts (but simpler than in 32-bit mode), add an extra argument to freevm (size of user part of address space) to avoid checking all entries till KERNBASE (there are MANY TB before the top 1TB). - x86: update trapframe to have 64-bit entries, which is what the processor pushes on syscalls and traps. simplify lgdt and lidt, using struct desctr, which needs the gcc directives packed and aligned. TODO: - use int32 instead of int? - simplify curproc(). xv6 has per-cpu state again, but this time it must have it. - avoid repetition in walkpgdir - fix validateint() in usertests.c - fix bugs (e.g., observed one a case of entering kernel with invalid gs or proc
76 lines
2 KiB
C
76 lines
2 KiB
C
// The I/O APIC manages hardware interrupts for an SMP system.
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// http://www.intel.com/design/chipsets/datashts/29056601.pdf
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// See also picirq.c.
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#include "types.h"
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#include "defs.h"
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#include "memlayout.h"
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#include "traps.h"
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#define IOAPIC 0xFEC00000 // Default physical address of IO APIC
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#define REG_ID 0x00 // Register index: ID
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#define REG_VER 0x01 // Register index: version
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#define REG_TABLE 0x10 // Redirection table base
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// The redirection table starts at REG_TABLE and uses
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// two registers to configure each interrupt.
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// The first (low) register in a pair contains configuration bits.
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// The second (high) register contains a bitmask telling which
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// CPUs can serve that interrupt.
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#define INT_DISABLED 0x00010000 // Interrupt disabled
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#define INT_LEVEL 0x00008000 // Level-triggered (vs edge-)
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#define INT_ACTIVELOW 0x00002000 // Active low (vs high)
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#define INT_LOGICAL 0x00000800 // Destination is CPU id (vs APIC ID)
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volatile struct ioapic *ioapic;
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// IO APIC MMIO structure: write reg, then read or write data.
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struct ioapic {
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uint reg;
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uint pad[3];
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uint data;
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};
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static uint
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ioapicread(int reg)
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{
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ioapic->reg = reg;
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return ioapic->data;
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}
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static void
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ioapicwrite(int reg, uint data)
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{
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ioapic->reg = reg;
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ioapic->data = data;
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}
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void
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ioapicinit(void)
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{
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int i, id, maxintr;
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ioapic = P2V((volatile struct ioapic*)IOAPIC);
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maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;
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id = ioapicread(REG_ID) >> 24;
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if(id != ioapicid)
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cprintf("ioapicinit: id isn't equal to ioapicid; not a MP\n");
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// Mark all interrupts edge-triggered, active high, disabled,
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// and not routed to any CPUs.
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for(i = 0; i <= maxintr; i++){
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ioapicwrite(REG_TABLE+2*i, INT_DISABLED | (T_IRQ0 + i));
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ioapicwrite(REG_TABLE+2*i+1, 0);
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}
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}
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void
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ioapicenable(int irq, int cpunum)
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{
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// Mark interrupt edge-triggered, active high,
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// enabled, and routed to the given cpunum,
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// which happens to be that cpu's APIC ID.
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ioapicwrite(REG_TABLE+2*irq, T_IRQ0 + irq);
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ioapicwrite(REG_TABLE+2*irq+1, cpunum << 24);
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}
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