162 lines
5.1 KiB
C
162 lines
5.1 KiB
C
// This file contains definitions for the
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// x86 memory management unit (MMU).
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// Eflags register
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#define FL_TF 0x00000100 // Trap Flag
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#define FL_IF 0x00000200 // Interrupt Enable
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// Control Register flags
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#define CR0_PE 0x00000001 // Protection Enable
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#define CR0_WP 0x00010000 // Write Protect
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#define CR0_PG 0x80000000 // Paging
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#define CR4_PSE 0x00000010 // Page size extension
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// Segment selectors (indexes) in our GDTs.
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// Defined by our convention, not the architecture.
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#define KCSEG32 (1<<3) /* kernel 32-bit code segment */
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#define KCSEG (2<<3) /* kernel code segment */
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#define KDSEG (3<<3) /* kernel data segment */
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#define TSSSEG (4<<3) /* tss segment - takes two slots */
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#define UDSEG (6<<3) /* user data segment */
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#define UCSEG (7<<3) /* user code segment */
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#define NSEGS 8
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#ifndef __ASSEMBLER__
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struct segdesc {
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uint16 limit0;
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uint16 base0;
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uint8 base1;
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uint8 bits;
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uint8 bitslimit1;
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uint8 base2;
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};
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// SEGDESC constructs a segment descriptor literal
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// with the given, base, limit, and type bits.
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#define SEGDESC(base, limit, bits) (struct segdesc){ \
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(limit)&0xffff, (base)&0xffff, \
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((base)>>16)&0xff, \
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(bits)&0xff, \
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(((bits)>>4)&0xf0) | ((limit>>16)&0xf), \
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((base)>>24)&0xff, \
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}
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// SEGDESCHI constructs an extension segment descriptor
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// literal that records the high bits of base.
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#define SEGDESCHI(base) (struct segdesc) { \
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(((base)>>32)&0xffff), (((base)>>48)&0xffff), \
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}
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#endif
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#define DPL_USER 0x3 // User DPL
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#define SEG_A (1<<0) /* segment accessed bit */
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#define SEG_R (1<<1) /* readable (code) */
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#define SEG_W (1<<1) /* writable (data) */
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#define SEG_C (1<<2) /* conforming segment (code) */
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#define SEG_E (1<<2) /* expand-down bit (data) */
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#define SEG_CODE (1<<3) /* code segment (instead of data) */
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// User and system segment bits.
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#define SEG_S (1<<4) /* if 0, system descriptor */
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#define SEG_DPL(x) ((x)<<5) /* descriptor privilege level (2 bits) */
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#define SEG_P (1<<7) /* segment present */
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#define SEG_AVL (1<<8) /* available for operating system use */
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#define SEG_L (1<<9) /* long mode */
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#define SEG_D (1<<10) /* default operation size 32-bit */
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#define SEG_G (1<<11) /* granularity */
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// Application segment type bits
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#define STA_X 0x8 // Executable segment
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#define STA_W 0x2 // Writeable (non-executable segments)
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#define STA_R 0x2 // Readable (executable segments)
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// System segment type bits
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#define SEG_LDT (2<<0) /* local descriptor table */
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#define SEG_TSS64A (9<<0) /* available 64-bit TSS */
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#define SEG_TSS64B (11<<0) /* busy 64-bit TSS */
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#define SEG_CALL64 (12<<0) /* 64-bit call gate */
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#define SEG_INTR64 (14<<0) /* 64-bit interrupt gate */
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#define SEG_TRAP64 (15<<0) /* 64-bit trap gate */
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// A virtual address 'la' has a six-part structure as follows:
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//
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// +--16--+---9---+------9-------+-----9----+----9-------+----12-------+
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// | Sign | PML4 |Page Directory| Page Dir |Page Table | Offset Page |
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// |Extend| Index | Pointer Index| Index | Index | in Page |
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// +------+-------+--------------+----------+------------+-------------+
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// L3 pgtab L2 pgtab L1 pgtab L0 pgtab
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// Page directory and page table constants.
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#define NPDENTRIES 512 // # directory entries per page directory
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#define PGSIZE 4096 // bytes mapped by a page
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#define PGSHIFT 12 // offset of PTX in a linear address
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#define PXMASK 0x1FF
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#define PXSHIFT(n) (PGSHIFT+(9*(n))) // shift for index into level n page table
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#define PX(n, va) ((((uint64) (va)) >> PXSHIFT(n)) & PXMASK)
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#define L_PML4 3
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#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1))
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#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1))
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// Page table/directory entry flags.
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#define PTE_P 0x001 // Present
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#define PTE_W 0x002 // Writeable
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#define PTE_U 0x004 // User
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#define PTE_PS 0x080 // Page Size
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#define PTE_PWT 0x008 // Write-Through
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#define PTE_PCD 0x010 // Cache-Disable
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// Address in page table or page directory entry
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#define PTE_ADDR(pte) ((uint64)(pte) & ~0xFFF)
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#define PTE_FLAGS(pte) ((uint64)(pte) & 0xFFF)
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#ifndef __ASSEMBLER__
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typedef uint64 pml4e_t;
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typedef uint64 pdpe_t;
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typedef uint64 pte_t;
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struct taskstate {
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uint8 reserved0[4];
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uint64 rsp[3];
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uint64 ist[8];
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uint8 reserved1[10];
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uint16 iomba;
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uint8 iopb[0];
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} __attribute__ ((packed));
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#define INT_P (1<<7) /* interrupt descriptor present */
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struct intgate
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{
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uint16 rip0;
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uint16 cs;
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uint8 reserved0;
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uint8 bits;
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uint16 rip1;
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uint32 rip2;
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uint32 reserved1;
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};
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// INTDESC constructs an interrupt descriptor literal
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// that records the given code segment, instruction pointer,
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// and type bits.
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#define INTDESC(cs, rip, bits) (struct intgate){ \
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(rip)&0xffff, (cs), 0, bits, ((rip)>>16)&0xffff, \
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(uint64)(rip)>>32, 0, \
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}
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// See section 4.6 of amd64 vol2
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struct desctr
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{
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uint16 limit;
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uint64 base;
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} __attribute__((packed, aligned(16))); // important!
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#endif
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