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CSRW/CSRS

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Imbus 2026-01-03 20:12:44 +01:00
parent 0d7d09dda3
commit dd8aed04c7
2 changed files with 95 additions and 0 deletions
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83
kern/libkern/riscv.h
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@ -18,6 +18,13 @@
#define SSTATUS_SIE (1L << 1) /** Supervisor Interrupt Enable */
#define SSTATUS_UIE (1L << 0) /** User Interrupt Enable */
// Machine Status Register, mstatus
#define MSTATUS_MPP_MASK (3L << 11) /** M-mode Previous Privilege */
#define MSTATUS_MPP_M (3L << 11) /** M-mode Previous Privilege Machine-mode */
#define MSTATUS_MPP_S (1L << 11) /** M-mode Previous Privilege Supervisor-mode */
#define MSTATUS_MPP_U (0L << 11) /** M-mode Previous Privilege User-mode */
#define MSTATUS_MIE (1L << 3) /** M-mode Interrupt Enable */
/** Page Table Entry Type */
typedef u64 pte_t;
@ -77,4 +84,80 @@ static inline int intr_get() {
return (x & SSTATUS_SIE) != 0;
}
/** Read Machine Exception Delegation */
static inline u64 r_medeleg() {
u64 x;
asm volatile("csrr %0, medeleg" : "=r"(x));
return x;
}
/** Write Machine Exception Delegation */
static inline void w_medeleg(u64 x) {
asm volatile("csrw medeleg, %0" : : "r"(x));
}
/** Read Machine Interrupt Delegation */
static inline u64 r_mideleg() {
u64 x;
asm volatile("csrr %0, mideleg" : "=r"(x));
return x;
}
/** Write Machine Interrupt Delegation */
static inline void w_mideleg(u64 x) {
asm volatile("csrw mideleg, %0" : : "r"(x));
}
static inline u64 r_mstatus() {
u64 x;
asm volatile("csrr %0, mstatus" : "=r"(x));
return x;
}
static inline void w_mstatus(u64 x) {
asm volatile("csrw mstatus, %0" : : "r"(x));
}
/** Supervisor External Interrup Enable */
#define SIE_SEIE (1L << 9)
/** Supervisor Timer Interrupt Enable */
#define SIE_STIE (1L << 5)
/** Supervisor Software Interrupt Enable */
#define SIE_SSIE (1L << 1)
/** Read the value of the sie register. (Supervisor Interrupt Enable) */
static inline u64 r_sie() {
u64 x;
asm volatile("csrr %0, sie" : "=r"(x));
return x;
}
/** Write the valie to the sie rgister. (Supervisor Interrupt Enable) */
static inline void w_sie(u64 x) {
asm volatile("csrw sie, %0" : : "r"(x));
}
/** Machine External Interrupt Enable */
#define MIE_MEIE (1L << 11)
/** Machine Timer Interrupt Enable */
#define MIE_MTIE (1L << 7)
/** Machine Software Interrupt Enable */
#define MIE_MSIE (1L << 3)
/** Read the value of the mie register. (Machine Interrupt Enable) */
static inline u64 r_mie() {
u64 x;
asm volatile("csrr %0, mie" : "=r"(x));
return x;
}
/** Write the value to the mie register. (Machine Interrupt Enable) */
static inline void w_mie(u64 x) {
asm volatile("csrw mie, %0" : : "r"(x));
}
#endif // RISCV_KERNEL_H