34 lines
2.8 KiB
Markdown
34 lines
2.8 KiB
Markdown
# Neptune Kernel
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Inspired by xv6
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For a quick reference on RISC-V assembly:
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- https://risc-v.guru/instructions/
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Toolchains:
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- https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
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- https://github.com/xpack-dev-tools/qemu-riscv-xpack/
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---
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> A word on terminology: Although the official x86 term is exception, xv6 uses the
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> term trap, largely because it was the term used by the PDP11/40 and therefore is the
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> conventional Unix term.
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| Register | Name | Privilege Level | Description |
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|-------------|----------------------------|------------------|-----------------------------------------------------------------------------|
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| `mstatus` | Machine Status Register | Machine | Holds global interrupt enable, previous privilege mode, etc. |
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| `mtvec` | Machine Trap-Vector Base | Machine | Holds the base address of the trap handler (exception/interrupt entry). |
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| `mepc` | Machine Exception PC | Machine | Stores the program counter at the time of the last trap. |
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| `mcause` | Machine Cause Register | Machine | Indicates the cause of the last trap (interrupt or exception). |
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| `satp` | Supervisor Address Translation and Protection | Supervisor | Controls page table base address and mode (e.g., Sv39, Sv48). |
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| `sstatus` | Supervisor Status Register | Supervisor | Like `mstatus`, but accessible from supervisor mode. |
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| `stvec` | Supervisor Trap-Vector Base| Supervisor | Like `mtvec`, but for supervisor mode traps. |
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| `sepc` | Supervisor Exception PC | Supervisor | Like `mepc`, but for supervisor mode. |
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| `scause` | Supervisor Cause Register | Supervisor | Like `mcause`, but for supervisor mode traps. |
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| `sscratch` | Supervisor Scratch | Supervisor | Can be used to store temporary state across traps in supervisor mode. |
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| `mscratch` | Machine Scratch | Machine | Like `sscratch`, but in machine mode. |
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| `mcycle` | Machine Cycle Counter | Machine | Counts the number of cycles executed. |
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| `mtime` | Machine Timer Register | Machine (via memory-mapped) | Used for timing and scheduling (not a CSR, but a memory-mapped register). |
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| `mip` | Machine Interrupt Pending | Machine | Indicates pending interrupts. |
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| `mie` | Machine Interrupt Enable | Machine | Controls which interrupts are enabled. |
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