Imbus/xv6-riscv-kernel
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Proper masking of the mtvec CSR word using macros.

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Imbus 2025-12-10 23:18:18 +01:00
parent 75264e130d
commit ed9505ae12
2 changed files with 12 additions and 2 deletions
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10
kernel/riscv.h
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@ -21,6 +21,16 @@ r_mhartid()
#define MSTATUS_MPP_U (0L << 11)
#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
#define MTVEC_MODE_DIRECT 0x0 // mtvec MODE values (RISC-V Privileged Spec)
#define MTVEC_MODE_VECTORED 0x1
#define MTVEC_MODE_MASK 0x3 // Mask for the MODE bits (bits [1:0])
// Align an mtvec base address (clear low 2 bits)
#define MTVEC_ALIGN(addr) ((uintptr_t)(addr) & ~MTVEC_MODE_MASK)
// Construct a complete mtvec value from BASE + MODE
#define MTVEC_VALUE(base, mode) (MTVEC_ALIGN(base) | ((mode) & MTVEC_MODE_MASK))
static inline u64
r_mstatus()
{

4
kernel/start.c
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@ -77,8 +77,8 @@ timerinit()
scratch[4] = interval;
w_mscratch((u64)scratch);
// Set the machine-mode trap handler.
w_mtvec((u64)timervec);
// Set the machine-mode trap handler. Set to direct, since scause is examined in the handler.
w_mtvec(MTVEC_VALUE((u64)timervec, MTVEC_MODE_DIRECT));
// Enable machine-mode interrupts.
w_mstatus(r_mstatus() | MSTATUS_MIE);