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0562c2fe5a
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265a388c93 |
4 changed files with 27 additions and 9 deletions
2
config.h
2
config.h
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@ -2,7 +2,7 @@
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* Number of CPU's For now, this is hard-coded here. It will likely be
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* dynamically discovered in the future.
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*/
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#define NCPU 3
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#define NCPU 4
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/* Maximum number of files open */
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#define NOFILE 10
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@ -19,7 +19,7 @@ void spin_unlock(spinlock_t *l) {
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// Optional: tiny pause/backoff (works even if Zihintpause isn't present).
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// See: https://github.com/riscv/riscv-isa-manual/blob/main/src/zihintpause.adoc
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void cpu_relax(void) {
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static inline void cpu_relax(void) {
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#if defined(__riscv_zihintpause)
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__asm__ volatile("pause");
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#else
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@ -8,5 +8,4 @@ typedef struct {
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void spinlock_init(spinlock_t *l);
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bool spin_trylock(spinlock_t *l);
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void spin_unlock(spinlock_t *l);
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void cpu_relax(void);
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void spin_lock(spinlock_t *l);
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31
start.c
31
start.c
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@ -18,9 +18,14 @@ char stack0[4096 * NCPU] __attribute__((aligned(16)));
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/* Keep this here and sync on it until we have synchronized printf */
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spinlock_t sl = {0};
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volatile int hold = 1;
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volatile int max_hart = 0;
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/* This is where entry.S drops us of. All cores land here */
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void start() {
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// Do this first
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__sync_fetch_and_add(&max_hart, 1);
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__sync_synchronize();
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u64 id = read_mhartid();
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// Keep each CPU's hartid in its tp (thread pointer) register, for cpuid().
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@ -35,15 +40,29 @@ void start() {
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uart_puts("Hello Neptune!\n");
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spinlock_init(&sl);
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hold = 0;
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} else {
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while (hold);
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}
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while (hold);
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// spin_lock(&sl);
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//
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// uart_puts("Hart number: ");
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// uart_putc(id + '0');
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// uart_putc('\n');
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//
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// spin_unlock(&sl);
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spin_lock(&sl);
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uart_puts("Hart number: ");
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uart_putc(id + '0');
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uart_putc('\n');
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spin_unlock(&sl);
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if (id == 0) {
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spin_lock(&sl);
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uart_puts("Core count: ");
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uart_putc(max_hart + '0');
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uart_putc('\n');
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if (max_hart == NCPU) {
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uart_puts("All cores up!");
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uart_putc('\n');
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}
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spin_unlock(&sl);
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}
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// We should not arrive here, but if we do, hang in a while on wfi.
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while (1) __asm__ volatile("wfi"); // (Wait For Interrupt)
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